1. Cross Reference to Other Applications
This is a continuation in part of application Ser. No. 07/106,750 filed Oct. 7, 1987, now U.S. Pat. No. 9,855,669 by Mahoney, entitled "System For Scan Testing of Logic Networks" whose disclosure is incorporated herein by reference.
2. Field of the Invention
The present invention relates to high density arrays of digital logic gates and more specifically to a structure and method for producing mask-interconnected integrated circuit substitutes for high density memory-configured logic arrays.
3. Description of the Prior Art
Advancements in the technology of integrated circuits have enabled designers to place relatively large numbers of digital logic gates on a single integrated circuit chip (IC) By way of example, so-called Large Scale Integration (LSI) and Very Large Scale Integration (VSLI) technologies give designers the ability to place roughly 1,000-9,000 or more logic gates on a standard size IC.
Numerous approaches have evolved for interconnecting the logic gates of such high density, digital logic IC's. A first approach, which may be described by terms such as "hard-wired interconnection", "metal interconnection", etc. and is referred to herein as "mask-configured interconnection" or more simply MCI, uses the fixed layout of various conductive paths in the IC, that are either diffused in the substrate or patterned in metallization layers of the IC, to interconnect input and output terminals of logic gates one to the next. Because the layout design of these paths is at the heart of the chip fabrication process, the MCI approach usually requires that employees at large-volume chip manufacturers (chip foundries) become intimately involved, not only with the design and fabrication of the metalized or diffused conductive lines themselves, but also with the logic flow of the overall digital circuit, the latter aspect being referred to sometimes as the "firmware" portion of the IC design. Such involvement by personnel of the chip manufacturer may be undesirable from the point of view of independent, application-specific type of firmware developers (ASIC developers) who often wish to use the chip manufacturer simply as a "silicon foundry" and do not wish to have the involvement of foundry personnel expand beyond a blind stamping out of mask-defined IC's. If access is granted to all portions of the IC design, proprietary portions of the firmware might be compromised.
In contrast to the MCI approach, there has evolved a second approach for interconnecting the logic gates of a high density digital IC, which may be described as "soft-wiring", "software configured interconnection", etc. and is referred to herein as "user-configured interconnection" or more simply UCI. The UCI approach allows chip manufacturers to sell generic chips that have arrays of predesigned logic function blocks (sometimes referred to as "configurable logic elements" (CLE's) or "configurable logic blocks" (CLB's)) and programmable interconnection portions (i.e., fusible links). The generic chips have user accessible programming pins which enable the chip purchaser (user) to programmably make or break connections in the programmable interconnection portions of the chips and to thereby define circuit paths between the logical function blocks. A desired firmware configuration can be "programmed" into the generic IC in either a volatile or nonvolatile manner without participation by the generic chip manufacturer or other parties.
Products belonging to the UCI approach include so-called "field programmable logic arrays" (FPLA's), "logic cell arrays" (LCA's) and "programmable logic devices" (PLD's). In these UCI types of products the chip user is given the option of programmably blowing a fusible link, shorting an antifuse, or activating a plurality of pass transistors whose individual ON/OFF states are controlled by an on-chip memory array. The UCI approach is advantageous in that, unlike the MCI approach, it allows the user to quickly develop application specific integrated circuits (ASIC's) without having to rely on an outside chip manufacturer for meeting production deadlines. The UCI approach is further advantageous in that it gives the user freedom to experiment with different firmware configurations, optimize the firmware design and keep the optimized firmware design as proprietary information. As such the UCI approach is more desirable than the MCI approach during initial phases of product development.
The UCI approach loses its advantage over the MCI approach in later phases of a product's life cycle when demand for the product grows and chips need to be produced in relatively large volumes (i.e., 1,000 units or more). The total cost of the product at such a point in its life cycle tends to be greater when the mass produced item is in the form of a user-configured IC rather than a mask configured chip. One reason user configurable chips have larger overall cost is that small-volume users of UCI chips generally do not possess the same type of expertise as large volume chip manufacturers in identifying and correcting numerous failure mechanisms which may develop in the mass production of IC's. A need exists for allowing users to develop their firmware designs in privacy at the early stages of product development, and at the same time, for allowing large volume manufacturers to quickly step in, generate mask interconnected substitutes for user developed devices, and exercise their expertise in fault identification and correction at later stages in product development when a design is taken from a prototype version to a mass production version.